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(R)
ISO-CMOS ST-BUSTM FAMILY
MT8980D
Digital Switch
Features
* * * * * * * * Mitel ST-BUS compatible 8-line x 32-channel inputs 8-line x 32-channel outputs MT8980DE MT8980DP
ISSUE8
March 1997
Ordering Information 40 Pin Plastic DIP 44 Pin PLCC
-40C to +85C
Description
256 ports non-blocking switch Single power supply (+5 V) Low power consumption: 30 mW Typ. Microprocessor-control interface Three-state serial outputs This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT8980 provides microprocessor read and write access to individual ST-BUS channels.
C4i
F0i
VDD
VSS
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Converter Data Memory
Frame Counter
Output MUX Parallel to Serial Converter
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
Control Register Connection Memory Control Interface
DS CS R/W A5/ A0
DTA D7/ D0
CSTo
Figure 1 - Functional Block Diagram
2-3
MT8980D
NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC
STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4
NC A3 A4 A5 DS R/W CS D7 D6 D5 NC
DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 A3 A4 A5 DS R/W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
44 PIN PLCC
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
40 DIP 44 PLCC
Name
Description
1
2
DTA
Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909 , 1/4W, resistor is recommended to be used as a pullup.
2-4 5-9 10 11
3-5 7-11 12 13
STi0- ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input STi2 streams. STi3- ST-BUS Input 3 to 7 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input STi7 streams. VDD F0i Power Input. Positive Supply. Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock.
12 1315 1618 19 20 21
14 1517 1921 22 23 24
C4i
A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor interface. A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface. DS R/W CS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. Chip Select (Input). This is the input for the active low chip select on the microprocessor interface
2-4
MT8980D
Pin Description (continued)
Pin #
40 DIP 44 PLCC
Name
Description
2224 2529 30 3135 3638 39
2527 2933 34 3539 4143 44
D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. VSS Power Input. Negative Supply (Ground).
STo7- ST-BUS Output 7 to 3 (Three-state Outputs). These are the pins for the eight 2048 STo3 kbit/s ST-BUS output streams. STo2- ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the eight 2048 STo0 kbit/s ST-BUS output streams. ODE Output Drive Enable (Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control. CSTo Control ST-BUS Output (Complementary Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. NC No Connection.
40
1 6, 18, 28, 40
2-5
MT8980D
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. In accordance with these trends, MITEL has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 s wide frames which contain 32 8-bit channels. MITEL manufactures a number of devices which interface to the ST-BUS; a key device being the MT8980 chip. The MT8980 can switch data from channels on STBUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs (Message Mode). To the microprocessor, the MT8980 looks like a memory peripheral. The microprocessor can write to the MT8980 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT8980, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the MT8980 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture. A5 0 1 1 * * * 1 A4 X 0 0 * * * 1 A3 X 0 0 * * * 1 A2 X 0 0 * * * 1 A1 X 0 0 * * * 1 A0 X 0 1 * * * 1 Hardware Description Serial data at 2048 kbit/s is received at the eight STBUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., MITEL's MT8964). This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory. LOCATION Control Register * Channel 0 Channel 1 * * * Channel 31
HEX ADDRESS 00 - 1F 20 21 * * * 3F
* Writing to the Control Register is the only fast transaction. Memory and stream are specified by the contents of the Control Register. Figure 3- Address Memory Map
2-6
MT8980D
The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8980s to be constructed. It also controls the CSTo pin. All ST-BUS timing is signals C4i and F0i. Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
(unused) Mode Control Bits Memory Select Bits Stream Address Bits
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST-BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values.
derived from the two
7
6
5
4
3
2
1
0
BIT 7
NAME Split Memory
DESCRIPTION When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output.
6
Message Mode (unused)
5 4-3
Memory 0-0 - Not to be used Select Bits 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High Stream Address Bits The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. Figure 4 - Control Register Bits
2-7
2-0
MT8980D
No Corresponding Memory - These bits give 0s if read.
Per Channel Control Bits
7
6
5
4
3
2
1
0
BIT 2
NAME Message Channel
DESCRIPTION When 1, the contents of the corresponding location in Connection Memory Low are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location's channel and stream. This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first. If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. Figure 5 - Connection Memory High Bits
1 0
CSTo Bit Output Enable
Stream Address Bits
Channel Address Bits
7
6
5
4
3
2
1
0
BIT 7-5*
NAME Stream Address Bits* Channel Address Bits*
DESCRIPTION The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4. The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
4-0*
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. Figure 6 - Connection Memory Low Bits
2-8
MT8980D
If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated STBUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-BUS input stream and channel where the byte is to be found (see Fig. 6). If the ODE pin is low, then all serial outputs are highimpedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5). Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output first in the channel; e.g., bit 1's for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0. Fig. 7 shows the interface between the MT8980s and the filter/codecs. Fig. 8 shows the position of these components in an example architecture. The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and ST-BUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT8980, which is used as a digital speech switch. The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT8980, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom MT8980. Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single MT8980 as a speech switch and a second MT8980 for communication with the line interface circuits. A larger digital switching system may be designed by cascading a number of MT8980s. Fig. 9 shows how four MT8980s may be arranged in a non-blocking configuration which can switch any channel on any of the ST-BUS inputs to any channel on the ST-BUS outputs.
Applications
Use in a Simple Digital Switching System Figs. 7 and 8 show how MT8980s can be used with MT8964s to form a simple digital switching system.
STo0 STi0 8980 used as speech switch
MT8980 DX DR DC STo0 STi0
MT8964 Filter/Codec
Signalling Logic
Line Driver and 2- to 4Wire Converter
8980 used in message mode for control and signalling
Line Interface Circuit with 8964 Filter/Codec MT8980
Figure 7 - Example of Typical Interface between 8980s and 8964s for Simple Digital Switching System
2-9
MT8980D
Line Interface Circuit with Codec (e.g. 8964) 8 Speech Switch 8980
STi0-7
Line 1
8
STo0-7
Controlling MicroProcessor
STo0-7
8
STi0-7
* * * Repeated for Lines 2 to 255
* * * Repeated for Lines 2 to 255
8 Control & Signalling 8980
Line Interface Circuit with Codec (e.g.8964)
Line 256
Figure 8 - Example Architecture of a Simple Digital Switching System Application Circuit with 6802 Processor Fig. 10 shows an example of a complete circuit which may be used to evaluate the chip. For convenience, a 4 MHz crystal oscillator has been used rather than a 4.096 MHz clock, as both are within the limits of the chip's specifications. The RC delay used with the 393 counters ensures a sufficient hold time for the FP signal, but the values used may have to be changed if faster 393 counters become available.
8980 #1 IN 0/7 STi0/7 STo0/7 OUT 0/7
The chip is shown as memory mapped into the MEK6802D3 system. Chip addresses 00-3F correspond to processor addresses 2000-203F. Delay through the address decoder requires the VMA signal to be used twice to remove glitches. The MEK6802D3 board uses a 10K pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a processor.
8980 #2 STi0/7 STo0/7 OUT 8/15
8980 #3 IN 8/15 STi0/7 STo0/7
8980 #4 STi0/7 STo0/7
Figure 9 - Four 8980s Arranged in a Non-Blocking 16 x 16 Configuration
2-10
MT8980D
D7-D0 A15-A0 MEK6802D3 System R/W
A15 A14 A13 0V 0V VMA 0V
1 2 3 4 5 6 7 8
MD 74 HCT 138
16 15 14 13 12 11 10 9
5V
MR VMA E A12 A11 A10 0V 0V 0V DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 A3 A4 A5 DS R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS 1 2 3 4 5 6 7 8 MD 74 HCT 138 16 15 14 13 12 11 10 9 5V
5V A9 A8 A7 0V 0V 0V 0V 1 2 3 4 5 6 7 8 MD 74 HCT 138 16 15 14 13 12 11 10 9 5V
909 , 1/4W 5V 5V
MT 8980
A6 VMA 0V 0V 0V 0V
1 2 3 4 5 6 7 8
MD 74 HCT 138
16 15 14 13 12 11 10 9
5V
C4i 0V
0V
1 2 3 4 5 6 7
SN 74 HCT 393
14 13 12 11 10 9 8
5V 0V
510
DTA CS 0V C4i 0V F0i 0V 0V
1 2 MD 3 74 4 HCT 5 240 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
5V 0V MR
5V
0V
0V
1 2 3 4 5 6 7
SN 74 HCT 393
14 13 12 11 10 9 8
5V
100pF
4 MHz
2M
Figure 10 - Application Circuit with 6802
2-11
MT8980D
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 6 VDD - VSS Voltage on Digital Inputs Voltage on Digital Outputs Current at Digital Outputs Storage Temperature Package Power Dissipation VI VO IO TS PD -65 Symbol Min -0.3 VSS-0.3 VSS-0.3 Max 7 VDD+0.3 VDD+0.3 40 +150 2 Units V V V mA C W
.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 Operating Temperature Positive Supply Input Voltage Sym TOP VDD VI Min -40 4.75 0 Typ Max +85 5.25 VDD Units C V V Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 O U T P U T S I N P U T S Supply Current Input High Voltage Input Low Voltage Input Leakage Input Pin Capacitance Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Output Pin Capacitance Sym IDD VIH VIL IIL CI VOH IOH VOL IOL IOZ CO 8 5 10 5 2.4 10 15 0.4 8 2.0 0.8 5 Min Typ 6 10 mA V V A pF V mA V mA A pF IOH = 10 mA Sourcing. VOH=2.4V IOL = 5 mA Sinking. VOL = 0.4V VO between VSS and VDD VI between VSS and VDD Outputs unloaded
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Test Point RL S1 CL VSS
VDD
S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VDD or VSS when testing output levels or high impedance states.
Output Pin
S2
VSS
Figure 11 - Output Test Load
2-12
MT8980D
AC Electrical Characteristics - Clock Timing (Figures 12 and 13)
Characteristics 1 2 3 4 5 6 7 I N P U T S Clock Period* Clock Width High Clock Width Low Clock Transition Time Frame Pulse SetupTime Frame Pulse Hold Time Frame Pulse Width Sym tCLK tCH tCL tCTT tFPS tFPH tFPW 20 0.020 244 Min 220 95 110 Typ 244 122 122 20 200 50 Max 300 150 150 Units ns ns ns ns ns s ns Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT CELLS
Channel 31 Bit o
Channel 0 Bit 7
Figure 12 - Frame Alignment
tCLK tCL 2.0V C4i 0.8V tCHL tFPH 2.0V F0i 0.8V tFPW tFPS tCTT tFPH tFPS tCTT tCH
Figure 13 - Clock Timing
2-13
MT8980D
AC Electrical Characteristics - Serial Streams (Figures 11, 14, 15 and 16)
Characteristics 1 2 3 4 5 6 7 8 9 I N O U T P U T S STo0/7 Delay - Active to High Z STo0/7 Delay - High Z to Active STo0/7 Delay - Active to Active STo0/7 Hold Time Output Driver Enable Delay External Control Hold Time External Control Delay Serial Input Setup Time Serial Input Hold Time Sym tSAZ tSZA tSAA tSOH tOED tXCH tXCD tSIS tSIH 90 0 Min 20 25 30 25 Typ 50 60 65 45 45 50 75 -40 110 -20 125 Max 80 125 125 Units ns ns ns ns ns ns ns ns ns Test Conditions RL=1 K*, CL=150 pF CL=150 pF CL=150 pF CL=150 pF RL=1 K*, CL=150 pF CL=150 pF CL=150 pF
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Bit Cell Boundary 2.0V 2.0V C4i 0.8V tSOH STo0 2.4V to STo7 0.4V tSAZ STo0 2.4V to STo7 0.4V ODE 0.8V
*
STo0 2.4V to STo7 0.4V
*
tOED tOED
*
*
tSZA tSOH
Figure 15 - Output Driver Enable
Bit Cell Boundaries 2.0V C4i 0.8V tSIH
STo0 2.4V to STo7 0.4V tSAA tXCH 2.4V CSTo 0.4V
STi0 2.0V to STi7 0.8V tSIS
tXCD
Figure 14 - Serial Outputs and External Control
2-14
Figure 16 - Serial Inputs
MT8980D
AC Electrical Characteristics - Processor Bus (Figures 11 and 17)
Characteristics 1 2 3 4 Chip Select Setup Time Read/Write Setup Time Address Setup Time Acknowledgement Delay Fast Slow 5 6 7 8 Fast Write Data Setup Time Slow Write Data Delay Read Data Setup Time Data Hold Time Read Write 9 10 11 12 13 Read Data To High Impedance Chip Select Hold Time Read/Write Hold Time Address Hold Time Acknowledgement Hold Time Sym tCSS tRWS tADS tAKD tAKD tFWS tSWD tRDS tDHT tDHT tRDZ tCSH tRWH tADH tAKH 0 0 0 10 60 80 20 20 10 50 90 2.7 20 2.0 1.7 0.5 Min 20 25 25 Typ 0 5 5 40 100 7.2 Max Units ns ns ns ns cycles ns cycles cycles ns ns ns ns ns ns ns RL=1 K, CL=150 pF RL=1 K, CL=150 pF C4i cycles C4i cycles, CL= 150 pF RL=1 K, CL=150 pF CL=150 pF C4i cycles Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. 2.0V DS 0.8V
2.0V CS 0.8V tCSS 2.0V R/W 0.8V tRWS A5 to A0 2.0V 0.8V tADS tAKD tAKH 2.4V DTA 0.4V tRDS D7 to D0 2.4V (Read) 2.0V (Write) 0.8V (Read 0.8V (Write) tDHT tADH tRWH tCSH
*
*
*
tSWD tFWS tRDZ
*
Figure 17 - Processor Bus
2-15
MT8980D
Notes:
2-16
Package Outlines
F
A G
D1 D
D2
H E E1 e: (lead coplanarity) A1 I E2 Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010"
20-Pin
Dim
28-Pin Min
0.165 (4.20) 0.090 (2.29) 0.485 (12.32)
44-Pin Min
0.165 (4.20) 0.090 (2.29) 0.685 (17.40)
68-Pin Min
0.165 (4.20) 0.090 (2.29) 0.985 (25.02)
84-Pin Min
0.165 (4.20) 0.090 (2.29) 1.185 (30.10)
Min
A A1 D/E D1/E1 D2/E2 e F G H I
0.165 (4.20) 0.090 (2.29) 0.385 (9.78) 0.350 (8.890) 0.290 (7.37) 0 0.026 (0.661) 0.013 (0.331)
Max
0.180 (4.57) 0.120 (3.04) 0.395 (10.03)
Max
0.180 (4.57) 0.120 (3.04) 0.495 (12.57)
Max
0.180 (4.57) 0.120 (3.04) 0.695 (17.65)
Max
0.200 (5.08) 0.130 (3.30) 0.995 (25.27)
Max
0.200 (5.08) 0.130 (3.30) 1.195 (30.35)
0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158 (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413) 0.330 (8.38) 0.004 0.032 (0.812) 0.021 (0.533) 0.390 (9.91) 0 0.026 (0.661) 0.013 (0.331) 0.430 (10.92) 0.004 0.032 (0.812) 0.021 (0.533) 0.590 (14.99) 0 0.026 (0.661) 0.013 (0.331) 0.630 (16.00) 0.004 0.032 (0.812) 0.021 (0.533) 0.890 (22.61) 0 0.026 (0.661) 0.013 (0.331) 0.930 (23.62) 0.004 0.032 (0.812) 0.021 (0.533) 1.090 (27.69) 0 0.026 (0.661) 0.013 (0.331) 1.130 (28.70) 0.004 0.032 (0.812) 0.021 (0.533)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
Package Outlines
3 2 1
E1
E
n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e b eB eC
Plastic Dual-In-Line Packages (PDIP) - E Suffix
8-Pin DIM Min A A2 b b2 C D D1 E E1 e eA L eB eC
0 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11)
16-Pin Plastic Max Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32)
18-Pin Plastic Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37)
20-Pin Plastic Min Max
0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52)
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
General-8
Package Outlines
3 2 1
E1
E
n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters)
A C eA
e b
eB
Plastic Dual-In-Line Packages (PDIP) - E Suffix
22-Pin DIM Min A A2 b b2 C D D1 E E E1 E1 e eA eA eB L
0.115 (2.93) 0.160 (4.06) 15 0.100 BSC (2.54) 0.400 BSC (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92)
24-Pin Plastic Max Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7)
28-Pin Plastic Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7)
40-Pin Plastic Min Max
0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2)
Plastic
0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.100 BSC (2.54) 0.600 BSC (15.24) 0.300 BSC (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08) 15
0.100 BSC (2.54) 0.600 BSC (15.24)
0.100 BSC (2.54) 0.600 BSC (15.24)
0.115 (2.93)
0.200 (5.08) 15
0.115 (2.93)
0.200 (5.08) 15
Shaded areas for 300 Mil Body Width 24 PDIP only
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